1. Field of the Invention
This invention relates to a process for growing a crystalline thin film to be used for electronic devices, optical devices, etc. of semiconductor integrated circuits. More particularly, it relates to a process for growing a crystalline thin film which can form the film at a relative lower temperature by controlling the nucleation positions of a plurality of thin film crystal grains, and can control also the position of the grain boundary and the sizes of crystal grains, etc.
2. Related Background Art
In the field of crystal formation technique which permits an amorphous thin film formed on a substrate having no crystallinity such as an amorphous substrate, etc. to grow in solid phase to a polycrystalline thin film by heat treatment at a temperature not higher than the melting point, there have been proposed some processes for making the grain sizes of the crystal grains constituting the polycrystalline thin film larger.
For example, there has been reported a crystal formation process, in which a polycrystalline Si thin film with fine grain sizes having a film thickness of about 1000.ANG. deposited by the LPCVD method on an amorphous SiO.sub.2 surface is made amorphous by implantation of Si.sup.+ ions, and then subjected to heat treatment in an N.sub.2 atmosphere at about 600 .degree. C., thereby making the above Si thin film as made amorphous a polycrystalline thin film with the maximum grain size of about 5 .mu.m (R. Reif and E. Knott, Electron. Lett. 17, 586 (1981)). Also in almost the same steps, by depositing the thin film previously in amorphous state and applying ion implantation thereinto, equal results are obtained (I. - W. Wu, A. Chiang, M. Fuse, L. Overcoglu and T. Y. Huang, J. Appl. Phys. 65, 4036 (1989)). Further, there is also a report that, by depositing the amorphous thin film previously at a further lower temperature, a polycrystalline thin film with grain sizes comparable to the foregoing two examples can be obtained without application of ion implantation.
When various electronic devices are formed on the polycrystalline thin films obtained by these processes, since the average grain size of the crystal grains is by far larger than conventional polycrystalline silicon, etc. as deposited by the LPCVD method, those with relatively higher performances can be obtained.
However, in these crystal formation processes, although the average grain size of the crystal grains of the thin film obtained are large, their grain size distribution and the position of the crystal grain boundary are not controlled. For, in this case, crystallization of the amorphous thin film takes place via the process in which crystal nuclei generated at random positions in the thin film grows along the plane direction while being restricted in growth in the film thickness direction to form flat crystal grains. Therefore the positions of the crystal grain boundaries formed at the contact points with the adjacent crystal grains are also randomly determined, whereby the grain sizes are distributed over a wide range. Accordingly, the following problems will ensue only if the average grain size of crystal grains is large. For example, when an MOS transistor is formed by use of the above polycrystalline film, if the average grain size becomes comparable with the size of channel, the situation becomes such that no grain boundary is included in the channel portion or that several or more boundaries are included. Crystal grain boundary will be a great obstacle against electroconduction, and therefore in the region where the number of grain boundaries included in the channel is 0 to several, the electrical characteristics will be greatly changed depending on the number of the grain boundaries included in the channel (N. Yamauchi, J. - J. J. Hajjar and R. Reif, IEDM 89-353 (1989)). For this reason, when an integrated circuits, etc. are formed, there occurs a great variance in the characteristics between a plurality of devices, which has been a remarkable obstacle in production of devices, etc.
Of the problems in the large grain size polycrystalline thin film by the solid phase crystallization as described above, the method of inhibiting variance of grain sizes is disclosed in Japanese Laid-Open Patent Application No. 58-56406. That method is described by referring to FIGS. 3A and 3B. First, as shown in FIG. 3A, on the surface of an amorphous Si thin film 12 formed on an amorphous substrate 11 are provided periodically thin film small strips 13 made of another material, followed by annealing of the substrate as a whole by a conventional heating furnace. Then, in the amorphous Si thin film 12, formation of crystal nuclei 14 will occur preferentially from the site in contact with the peripheral of the thin film small strip 13. Accordingly, by growing further the crystal nuclei, the amorphous Si thin film 12 will be crystallized over the whole region, whereby a polycrystalline thin film comprising the crystal grain groups 15 with large sizes as shown in FIG. 3B is obtained. Japanese Laid-Open Patent Application No. 58-56406 states that the variance of grain sizes can be reduced to about 1/3 as compared with the prior art method previously shown.
However, even such method is still unsatisfactory. For example, when thin film small strips 13 are arranged in lattice points with intervals of 10 .mu.m, the variance of grain sizes can be limited only to the range of 3 to 8 .mu.m. Further, the crystal grain boundary position is not easily controlled under the present situation. The reason is that due to the localization effect of elastic energy at the portion where the amorphous Si thin film 12 is in contact with the peripheral portion of the thin film small strip 13, preferential nucleation occurs around the thin film small strip 13, whereby a plurality of nuclei will be generated along the peripheral, and their number is difficult to control.
Concerning the method of controlling the nucleation position in the solid phase growth of amorphous Si thin film, Japanese Laid-Open Patent Application No. 63-253616, etc. discloses other proposals. According to the method disclosed in the publication, as shown in FIG. 4, regions 23 are provided by implanting N.sup.+ ions locally into the amorphous Si thin film 22 in the direction shown by the arrowhead A in the figure, and crystal nuclei are generated preferentially from the portions other than the regions 23. In the figure, 21 designates an amorphous substrate.
Further, for inhibiting variance of crystal grain sizes by arranging regularly the crystal grains having larger sizes and controlling the grain boundary positions, not only the regions where crystal nuclei are preferentially formed should be provided within the plane of the amorphous thin film, but at the same time in the areas around those regions, spontaneous nucleation must be inhibited while ensuring sufficient crystal growth rate. For example, in the method of Japanese Laid-Open Patent Application No. 58-56406, even if only a single crystal-nucleus may happen to be formed around the thin film small strip 13, if random nucleation has occurred in the film until it has reached 8 .mu.m at the maximum as the grain size, its growth will be inhibited, whereby growth to a crystal grain with larger grain size than that is very difficult.
As described above, so many problems to be overcome have existed in the techniques proposed in the prior art.